﻿inverter_tran_Corners.ocn                        //simulate low Vdd sleep mode butterfly curves
block_sim.ocn                                        //simulate reading delay on model block 
vth_snm.ocn                                                   //corner test file for VTH model
hold-butterfly-netlist                                        //Netlist for bufferfly curves
 
Simulation results:
jietu.png  (write simulation)
 
TB_ECC_netlist, ECC_ocn.ocn                //files for producing ECCsimulation-trans.png
memblock_netlist, memblock_ocn.ocn        //files for simulating for power of memory blocks                                                                 with added bitcells for ECC.